HARON, N.; DARSONO, A.; M.ISA, A. High Performance, Fault Tolerance Architecture for Reliable Hybrid Nanometric Memories. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), [S. l.], v. 4, n. 2, p. 1–10, 2015. Disponível em: https://jtec.utem.edu.my/jtec/article/view/430. Acesso em: 29 apr. 2024.