AHMATAKU, H.; MOHAMADDAN, S.; WARREN, E.; YUSUF, M.; ALIAS, A. A.; ABDUL MANAS, N. H.; KIPLI, K. Analysis of Gate Poly Delayering in SOI Wafer. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), [S. l.], v. 10, n. 1-12, p. 85–87, 2018. Disponível em: https://jtec.utem.edu.my/jtec/article/view/3831. Acesso em: 5 may. 2024.