S. RIBLE, G.; SABATE, M. C. I.; HORA, J. A. Low Power Design of MPPT Circuit Using Power Down System in 65nm CMOS Process. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), [S. l.], v. 10, n. 1, p. 45–50, 2018. Disponível em: https://jtec.utem.edu.my/jtec/article/view/1933. Acesso em: 7 may. 2024.