KAHARUDIN, K.; SALEHUDDIN, F.; ZAIN, A.; A. AZIZ, M. Implementation of Taguchi Method for Lower Drain Induced Barrier Lowering in Vertical Double Gate NMOS Device. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), [S. l.], v. 8, n. 4, p. 11–16, 2016. Disponível em: https://jtec.utem.edu.my/jtec/article/view/1196. Acesso em: 28 may. 2024.