CHEK YEE, O.; SOO KING, L. Simulation Study on Different Logic Families of NOT Gate Transistor Level Circuits Implemented Using Nano-MOSFETs. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), [S. l.], v. 8, n. 5, p. 61–67, 2016. Disponível em: https://jtec.utem.edu.my/jtec/article/view/765. Acesso em: 22 dec. 2024.