HASHIZUME, M.; SHIRAISHI, Y.; YOTSUYANAGI, H.; YOKOYAMA, H.; TADA, T.; LU, S.-K. Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), [S. l.], v. 9, n. 3-2, p. 39–42, 2017. Disponível em: https://jtec.utem.edu.my/jtec/article/view/2810. Acesso em: 22 dec. 2024.