Hashizume, M., Shiraishi, Y., Yotsuyanagi, H., Yokoyama, H., Tada, T., & Lu, S.-K. (2017). Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 9(3-2), 39–42. Retrieved from https://jtec.utem.edu.my/jtec/article/view/2810