H.R, A., Byrareddy, C. R., & C. P, N. (2020). Design of an Efficient AXI-4 Protocol for High Speed SOC Applications on FPGA Platform. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 12(3), 61–68. https://doi.org/10.54554/jtec.2020.12.03.010