[1]
Z. A, N.F., Ahmad, I., Ker, P., Menon, P. and A.H., A.M. 2017. VTH and ILEAK Optimization Using Taguchi Method at 32nm Bilayer Graphene PMOS. Journal of Telecommunication, Electronic and Computer Engineering (JTEC). 9, 2-7 (Sep. 2017), 105–109.