@article{Shafiabadi_Mehrabani_2016, title={A Novel Ultra Low-Power 10T CNFET-Based Full Adder Cell Design in 32nm Technology}, volume={8}, url={https://jtec.utem.edu.my/jtec/article/view/831}, abstractNote={Nowadays, energy consumption is the main concern in portable electronic systems such as laptops, smart mobile phones, personal digital assistances (PDAs) and so forth. Considering that the 1-bit Full adder cell has been the determinant circuit due to its wide usage in these systems, it affects the entire performance of the electronic system. In this paper, a novel low-power and low-energy 10 transistor (10T) Full Adder cell using NAND/NOR functions based on carbon nanotube field effect transistors (CNFETs) is presented. The proposed cell showed superiority in terms of power-delay product (PDP) compared to the other cells under different simulation condition, such as power supply, temperature, load and operating frequency variations. Moreover, a Monte Carlo (MC) simulation was conducted to study the reliability of the proposed cell against manufacturing process variations (i.e. the variations of diameters of carbon nanotubes). Simulations confirmed the robustness of the proposed cell.}, number={9}, journal={Journal of Telecommunication, Electronic and Computer Engineering (JTEC)}, author={Shafiabadi, Mohammad Hossein and Mehrabani, Yavar Safaei}, year={2016}, month={Dec.}, pages={25–30} }