@article{Omidi_Eidi_Mohammady_Torabi_2016, title={Reliability and Performance Analysis of a Fault Tolerant Data Handling Protocol for Aerospace Applications}, volume={7}, url={https://jtec.utem.edu.my/jtec/article/view/609}, abstractNote={<span style="font-size: 11pt; font-family: ’Calibri’,’sans-serif’; line-height: 115%; mso-fareast-font-family: Calibri; mso-bidi-font-family: ’Times New Roman’; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA;">Data communication inside the satellite is one of the most important factors in satellite design. For this purpose, a variety of protocols have been developed in recent years. Controller Area Network (CAN) is one of the well-developed protocols to be used in the On-Board Data Handling (OBDH) systems for communication and geosynchronous satellites. Nonetheless, for aerospace applications which demand radiation hardened integrated circuits, a full featured stand-alone Rad-Hard CAN controller is unavailable. HDL (Hardware Description Language) based IP</span><span style="font-size: 11pt; font-family: ’Calibri’,’sans-serif’; line-height: 115%; mso-fareast-font-family: Calibri; mso-bidi-font-family: ’Times New Roman’; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA;">(Intellectual Property) Cores which are widely developed to be implemented on Rad-Hard FPGAs are more attractive. This paper proposes a novel fault tolerant CAN controller based on FPGAs to provide on-board data handling requirements of the communication satellites. We outline some practical topologies and discuss their complexities and reliability. Despite the fact that the most famous methods like TMR (Triple Modular Redundancy), are very common among designers, the reliability analyses show that these methods are unable to tolerate single upsets in routing matrixes. This paper proposes a robust data bus controller based on dual duplex redundancy on FPGAs. The fault injection experiments reveal that the proposed approach represents better performance respective to the conventional hardware redundancy. Furthermore, the experiments show that the capability of tolerating SEU effects by the proposed method is increased up to 7.17 times with respect to a regular design. The proposed architecture imposes 16.26% and 5.2% overhead in the required resources and the operating frequency in comparison to the regular TMR method.</span>}, number={2}, journal={Journal of Telecommunication, Electronic and Computer Engineering (JTEC)}, author={Omidi, R. and Eidi, A. and Mohammady, L. and Torabi, S.Y.}, year={2016}, month={Feb.}, pages={19–26} }