Current-Voltage Analysis of Nanoscale Planar and Vertical MOSFT Incorporating Dielectric Pocket

Authors

  • Z.A.F. M. Napiah
  • A.S Ja'afar
  • I. Saad
  • M.A Riyadi
  • R. Ismail

Keywords:

Vertical, Planar, dielectric pocket, SCE, DIBL

Abstract

Characterization of nanoscale planar and vertical metal-oxide-semiconductor field effect transistor incorporating dielectric pocket (DP-MOSFET) is demonstrated by using numerical simulation. Vertical MOSFET is one solution to shrink the channel length (L g ) into nanometer regime. The comparison between planar and vertical MOSFET was done to show an advantages of dielectric pocket and each performances in current-voltage analysis. Dielectric pocket is incorporated between the channel and source/drain for suppression of short-channel effects (SCE) and bulk punchthrough. The current-voltage analysis for both structure shows rational value of threshold voltage (V T ), drive current (I ON ), off-state leakage current (I OFF ), subthreshold swing (S) and Drain Induced Barrier Lowering (DIBL). A better control of VT roll-off was also demonstrated by incorporation of DP and better for vertical MOSFET compared to planar MOSFET. Thus, the incorporation of DP will enhance the electrical performance and give a very good control of the SCE for scaling the MOSFET in nanometer regime for future development of nanoelectronics product

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How to Cite

M. Napiah, Z., Ja’afar, A., Saad, I., Riyadi, M., & Ismail, R. (2011). Current-Voltage Analysis of Nanoscale Planar and Vertical MOSFT Incorporating Dielectric Pocket. Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 3(2), 41–45. Retrieved from https://jtec.utem.edu.my/jtec/article/view/424

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Articles