The Impact of Soft Error On C-Element with Different Technology

Abstract

This paper presents current injection resemble single event upset (SEU) current at the vulnerable nodes on Celements in particular Single Inverter with Inverter Latch (SIL) under two different technology 90nm and 180nm. C-element mainly uses in asynchronous circuits as the demand of consuming low power continue to become more important compared with synchronous circuits. However, one of the problems of asynchronous circuits is that they stay sensitive to SEU continuously for the whole cycle of operation. For asynchronous circuits, an acknowledgement signal is sent to the preceding register after the current operation is finished, indicating it is ready for the next operation. In the event of SEU hitting one of the registers, no acknowledgement signal is sent and therefore the preceding register does not assign the next operation to the current computational block. It is observed that the size of the transistor is the most important factors of critical charge variation since it has the highest standard deviation compared with temperature. This is due to the increasing the size of the transistors increases the gate capacitance from the output and therefore the collected charge needed to flip the output is also larger. However, as the size of the circuit is bigger, the probability of hitting by SEU is also increased even though the circuit is more resistant against SEU. The least significant factor is the temperature. As the temperature increased, the mobility of the carrier is reduced and degrades the performance of the transistor.